Multiplier-less Multiplication by Constants - Digital Design of Signal Processing Systems: A Practical Approach - page 265

The computed CV 1 for the second coefficient is shown in Figure 6.7, and so:

32 0 b CV 1 ¼ 1101 1110 0000 0000 0000 0100 0000 0000

Following the same procedure, the CV 2 computes to:

32 0 b CV 2 ¼ 1011 1101 1011 1000 0000 0100 1001 0000

Because of symmetry of the coefficients, CV 3 and CV 4 are the same as CV 1 and CV 0 , respectively.
All these correction vectors are added to get the GCV:

32 0 b

GCV ¼ 01101111011100000001000010010000

This correction vector is added for sign-extension elimination.
The implementation of three designs in RTL Verilog is given in this section. The
module FIRfilter uses multipliers and adders to implement the FIR filter, whereas module
FIRfilterCSD converts the filter coefficients in CSD format while considering a maximumof four
non-zero CSD digits for each coefficient. There are a total of 16 PPs that are generated and added to
show the equivalence of the design with the original format. The code simply adds the PP whereas,
in actual designs, the PPs should be compressed usingWallace or Dadda reduction schemes. Finally,
the module FIRfilterCV implements sign-extension elimination logic by computing a GCV.
The vector is added in place of all the sign bits and 1s that are there to cater for two's complement in
the PPs. The Verilog code of the three modules with stimulus is listed here.

// Module uses multipliers to implement an FIR filter
module FIRfilter(
input signed [15:0] x,
input clk,
output reg signed [31:0] yn);
reg signed [15:0] xn [0:4];
wire signed [31:0] yn_v;

// Coefficients of the filter
wire signed [15:0] h0 = 16 ' h0325;
wire signed [15:0] h1 = 16 ' h1e00;
wire signed [15:0] h2 = 16 ' h3DB6;
wire signed [15:0] h3 = 16 ' h1e00;
wire signed [15:0] h4 = 16 ' h0325;

// Implementing filters using multiplication and addition operators
assign yn_v = (h0*xn[0] + h1*xn[1] + h2*xn[2] + h3*xn[3] + h4*xn[4]);
always @(posedge clk)
begin

// Tap delay line of the filter
xn[0] <= x;
xn[1] <= xn[0];