Overview - Digital Design of Signal Processing Systems: A Practical Approach - page 6

Control Panel

ASIC

Controller Sequence

GPP

ASIC

User interface
application

Shared Bus

FPGA

DSP DSP CODEC

FPGA

Shared Memory

RF Interface

Figure 1.3 An embedded signal processing system with DSPs, FPGAs, ASICs and GPP

The digital design of a digital communication system interfaces with the RF front end. For voice-
based applications the system also contains CODEC (more in Chapter 12) with associated analog
interfaces. The FPAGs in the system also provide glue logic and interfaces with other devices in the
system. There may also be dual-port RAM to provide shared memory to multiple DSPs in the
system. A representative system is shown in Figure 1.3.

1.3.2 Multi-core Systems
Many applications are best mapped on general-purpose processors. As high-end computing applica-
tions demandmore andmore computational power in programmable devices, the vendors of GPPs are
incorporating multiple cores of GPPs in a single SoC configuration. Almost all the vendors of GPPs,
such as Intel, IBM, Sun Microsystems and AMD, are now placing multiple cores on a single chip for
improved performance and high reliability. Examples are Intel's Yorkfield 8-core chip in 45-nm
technology, Intel's 80-core teraflop processor, Sun's Rock 8-core CPU, Sun's UltraSPARCT1 8-core
CPU, and IBM's 8-core POWER7. These multi-core solutions also offer the necessary abstraction,
whereby the programmer need not be concerned with the underlying complex architecture, and
software development tools have been produced that partition and map applications on these
multiple cores. This trend is continuously adding complexity to digital design and software tool
development. From the digital design perspective, multi processors based systems are required to