Design Options for Basic Building Blocks - Digital Design of Signal Processing Systems: A Practical Approach - page 246

Op 1 Op 2 Op 1 Op 3

Op 1 Op 2 Op 3

PP
Generation

PP
Generation

+

Compression Tree

x

CPA

y

Figure 5.53 Transforming the add and multiply operation to use one CPA and a compression tree

This representation of the expression now requires one compression tree that is then followed by
one CPA to compute the final value. The associated DFG and the transformation are shown in
Figure 5.53.
Extending the technique of generating partial sums and carries can optimize hardware imple-
mentation of a cascade of multiplications as well:

prod ¼ op 1 op 2 op 3 op 4

The transformation first generates PPs for op1 op2 and reduces them to two PPs, s1 and c1:

ð Þ¼op s 1

; c

1 1 op 2

These two PPs independently multiply with op3, which generates two sets of PPs that are again
reduced to two PPs, s2 and c2, using a compression tree:

ð Þ¼s s 2

; c

2 1 op 3 þc 1 op 3

These two PPs further multiply with op4 to generate two sets of PPs that are again compressed to
compute the final two PPs, s3 and c3. These two PPs are then added using a CPA to compute the final
product:

ð Þ¼s s 3

; c

3 2 op 4 þc 2 op 4

prod ¼ s 3 þc 3

The equivalent transformation on a DFG is illustrated in Figure 5.54.
Following these examples, several transformations using basic mathematical properties can be
used to accumulate several operators for effective use of compression trees for optimized hardware
mapping.