Design Options for Basic Building Blocks - Digital Design of Signal Processing Systems: A Practical Approach - page 240

9

2a

a
-a

CV

-2a

0 3

b0
b1

BR0 3-5

Wallace Tree
Reduction
Scheme

a

2a 0 -a -2a

3

b2
b3

BR1 3-5

16 Bit
CSA

3

b4
b5

BR2 3-5

16

3

BR3 3-5

b6
b7

Figure 5.48 An 8 8-bit modified Booth recoder multiplier

5.9.5 Modified Booth Recoded Multiplier in RTL Verilog
The example here implements a 6 6-bit MBR multiplier. The three components in the design are

Booth recoder, CV generation and PPs accumulation. The design is implemented in Verilog and
code is listed at the end of this chapter. AVerilog function RECODERfn implements the recoding
part. It divides the 6 bits of the multiplier into three groups of 2 bits each. RECODERfn takes three
bits as input, consisting of two bits of each group and the MSB of the previous group, and generates
one of the five values 0, 1, 2 as output. AVerilog task, GENERATE_PPtk , generates three

PPs with sign-extension elimination and a CV for the design. In cases where the recoded value is 2 or

1, 2 or

2, the PP is generated by shifting the multiplicand or its compliment by 1 to the left, and this
requires the PP to be 7 bits wide. For all other cases the seventh bit is the sign bit of the multiplicand.
Sign-extension elimination logic is implemented. This requires flipping the MSB of the PP. For the
cases of multiplication by 1or 2, two's complement of the PP is computed by flipping all the bits
and adding 1 to the LSB location. The addition of 1 is included in the CV, and the vector is appended
by 2 0 b01 for multiplication by 1 and 2 0 b10 for multiplication by 2, as in this case the LSB is
shifted by one bit position to the left. The output of the task is three PPs and six LSBs of the CV. The
sign-extension elimination logic for the three PP is precalculated. By adding all the sign-extension
elimination bits we get the five MSBs of the CV as 5 0 b01011 as shown in Figure 5.49.
The code below illustrates the implementation of Booth recoding and sign-extension elimination
logic in RTLVerilog. As the focus of the example is to illustrate the MBR technique, it simply adds
all the PPs and the CV to compute the product. As the PPs and CV form four layers, for optimized

1 0 1 0 1
1 1 1 1

s

s

1 1

s
0 1 0 1 1

Figure 5.49 Pre-calculated part of the CV