Design Options for Basic Building Blocks - Digital Design of Signal Processing Systems: A Practical Approach - page 236

(a)

flip the sign bit

extend all 1s

B=0 0 0 0 0 0.1 1 0 1 0 1 1
B= 1 1 1 1 1 0 .1 1 0 1 0 1 1

+ add 1 at the location of sign bit

1

0 0 0 0 0 0.1 1 0 1 0 1 1

(b)

flip the sign bit

extend all 1s

B=1 1 1 1 1 1.1 1 0 1 0 1 1
B= 1 1 1 1 1 1 .1 1 0 1 0 1 1

+ 1 add 1 at the location of sign bit

1 1 1 1 1 1.1 1 0 1 0 1 1

Figure 5.43 Sign-extension elimination

sign-bit location and extended bits are replaced by all 1s. This technique equivalently working on
negative numbers is shown in Figure 5.43(b). The sign-bit 1 is flipped to 0 and a 1 is added to the sign-
bit location and the extended bits are all 1s. Thus, irrespective of the sign of the number, the
technique makes all the extended bits into 1s. Now to eliminate the sign extension logic, all these 1s
are added off-line to form a correction vector.
Figure 5.44 illustrates the steps involved in sign-extension elimination logic on a 11 6-bit
signed by signed multiplier. First the MSB of all the PPs except the last one are flipped and a 1 is
added at the sign-bit location, and the number is extended by all 1s. For the last PP, the two's
complement is computed by flipping all the bits and adding 1 to the LSB position. The MSB of the
last PP is flipped again and 1 is added to this bit location for sign extension. All these 1s are added to
find a correction vector (CV). Now all the 1s are removed and the CV is simply added and it takes
care of the sign extension logic.
Example: Find the correction vector for a 4 4-bit signed multiplier and use the CV to multiply

two numbers 0011 and 1101. In Figure 5.45(a), all the 1s for sign extension and two's complement
are added and CV

0001_0000. Applying sign-extension elimination logic and adding CV to the
PPs, themultiplication is performed again and it gives the same result, as shown in Figure 5.45(b). As
the correction vector has just one non-zero bit, the bit is appended with the first PP (shown in gray).

¼

111111
11111 S XXXXXXXXXX
1111 S XXXXXXXXXX
111 S XXXXXXXXXX
11 S XXXXXXXXXX
1 S XXXXXXXXXX
S XXXXXXXXXX

1 1 1 1 1 1
1 1 1 1 1
1 1 1 1
1 1 1
1 1
1
0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0

1

1's complement
and adding 1
at LSB

1

Figure 5.44 Sign-extension elimination and CV formulation for signed by signed multiplication