Design Options for Basic Building Blocks - Digital Design of Signal Processing Systems: A Practical Approach - page 233

CPA

CPA

Figure 5.37 Counters compressing a 15 15 matrix

GPCoffers flexibility oncemapped on to a FPGA. The problemof configuring dimensions of GPC
for mapping on FPGA for multi-operand addition is anNP-complete problem. The problem is solved
using 'integer programming', and the method is reported to outperform adder tree-based imple-
mentation from the area and timing perspectives [18].
As stated earlier, FGPAs are best suited for counters and GPC-based compression trees. To fully
utilize 6-LUT-based FPGAs, it is better that each counter or GPC should have six input bits and three
(or preferably four) output bits, as shown in Figures 5.40 and 5.41. The four output bits are favored as

Figure 5.38 A (3,4,5:5) GPC compressing three columns with 3, 4 and 5 bits to 5 bits in different
columns