Design Options for Basic Building Blocks - Digital Design of Signal Processing Systems: A Practical Approach - page 231

5.8.5 Optimized Compressors
Based on the concept of CSA, several other compressor blocks can be developed. For example a 4:2
compressor takes four operands and 1 bit for the carry-in and reduces them to 2 bits in addition to a
carry-out bit. A candidate implementation of the compressor is shown in Figure 5.35(a). While
compressing multiple operands the compressor works in cascade and creates an extended tile, as
shown in Figure 5.35(b).
The use of this compressor in Wallace and Dadda reduction trees for an 8 8-bit multiplier is
shown in Figures 5.35(c) and (d). This compressor, by using carry-chain logic, is reported to exhibit
better timing and area performance compared with a CSA-based compression on a Virtex
FGPA [14]. Similarly, a 5:3 bit counter reduces 5 bits to 3 bits with a carry-in and carry-out bit
and is used in designing multiplier architectures in [15].

( 3,2 ) ( 3,2 ) ( 3,2 ) ( 3,2 )

c_out

c_in

( 3,2 ) ( 3,2 ) ( 3,2 )

( 3,2 )

(a) (b)

(c) (d)

Figure 5.35 (a) Candidate implementation of a 4:2 compressor. (b) Concatenation of 4:2 compression to
create wider tiles. (c) Use of a 4:2 compressor inWallace tree reduction of an 8 8 multiplier. (d) Use of a
4:2 compressor in an 8 8 multiplier in Dadda reduction