Design Options for Basic Building Blocks - Digital Design of Signal Processing Systems: A Practical Approach - page 224

6 unsigned multiplier is given below. The implementation only highlights
the partial product generation and does not use any PP reduction techniques. These PPs are
appropriately shifted by using a concatenation operator in Verilog and then added to complete the
functionality of the multiplier module. The second technique of partial product generation, called
modified Booth recoding, is discussed in Section 5.9.4.

Verilog code for a 6

module multiplier
(
input [5:0] a,b,
output [11:0] prod);
integer i;
reg [5:0] pp [0:5];//6 partial products
always@*
begin
for(i=0; i<6; i=i+1)
begin
pp[i] = b & {6{a[i]}};

end

end

assign prod = pp[0]+{pp[1],1'b0}+{pp[2],2'b0} +
{pp[3],3'b0}+{pp[4],4'b0}+{pp[5],5'b0};

endmodule

5.8.3 Partial Product Reduction
WhilemultiplyinganN 1 -bitmultiplierawithanN 2 -bitmultiplicandb,N 1 PPsareproducedbyANDing
eachbit a[i]of themultiplierwithall thebitsof themultiplicandandshifting thepartial productPP[i]to
the left by i bit positions. Using dot notations to represent bits, all the partial products form a
parallelogram array of dots. These dots in each column are to be added to compute the final product.
For a general N 1 N 2 multiplier, the following four techniques are generally used to reduce N 1

layers of the partial products to two layers for their final addition using any CPA:

. carry save reduction
. dual carry save reduction
. Wallace tree reduction
. Dadda tree reduction.

Although the techniques are described here for 3:2 compressors, the same can be easily extended for
other compressors and counters.

5.8.3.1 Carry Save Reduction

The first three layers of the PPs are reduced to two layers using carry save addition (CSA). In this
reduction process, while generating the next level of logic, isolated bits in a column, in the selected
three layers, are simply dropped down to the same column, columns with two bits are reduced to two
bits using half adders and the columns with three bits are reduced to two bits using full adders. While
adding bits using HAs or FAs, the dot representing the sum bit is dropped down in the same column
whereas the dot representing the carry bit is placed in the next significant bit column. Once the first
three partial products are reduced to two layers, the fourth partial product in the original composition