Design Options for Basic Building Blocks - Digital Design of Signal Processing Systems: A Practical Approach - page 220

a barrel shifter is given in Figure 5.23(b), and the code for RTLVerilog implementation of the design
is listed here:

module BarrelShifterPipelined(
input clk,
input [15:0] x,
input signed [4:0] s,
input A_L,
output reg [15:0]y);
reg [30:0] y0, y0_reg;
reg [22:0] y1, y1_reg;
reg [18:0] y2, y2_reg;
reg [16:0] y3, y3_reg;
reg [14:0] sgn;
reg [3:0] s_reg;
reg [2:0] sp_reg;
reg [1:0] spp_reg;
reg sppp_reg;

always @(*)
begin
// A_L =1 for arithmetic and 0 for logical shift
sgn = (A_L) ? {15{x[15]}} : 15'b0;
y0 = (s[4]) ? {x[14:0],16'b0} : {sgn[14:0], x[15:0]};
y1 = (s_reg[3]) ? y0_reg[30:8] : y0_reg[22:0];
y2 = (sp_reg[2]) ? y1_reg[22:4] : y1_reg[18:0];
y3 = (spp_reg[1]) ? y2_reg[18:2] : y2_reg[16:0];
y = (sppp_reg) ? y3_reg[16:1] : y3_reg[15:0];

end
always @ (posedge clk)
begin
y0_reg <= y0;
y1_reg <= y1;
y2_reg <= y2;
y3_reg <= y3;
s_reg <= s[3:0];
sp_reg <= s_reg [2:0];
spp_reg <= sp_reg [1:0];
sppp_reg <= spp_reg [0];

end
endmodule

A barrel shifter can also be implemented using a dedicatedmultiplier in FPGAs. A shift by s to the
left is multiplication by 2 s , and similarly a shift to the right by s is multiplication by 2 s .To
accomplish the shift operation, the number can be multiplied by an appropriate power of 2 to get the
desired shift.
Example: Assume x is a signed operand in Q1.7 format. Let:

x ¼ 8 0 1001 0101

2 3 , which in Q1.7 format is equivalent to
y ¼ 8 0 b0001_0000. The fractional multiplication of x by y results in a Q2.14 format number:

x 3 can be performed by multiplying x by y ¼