Design Options for Basic Building Blocks - Digital Design of Signal Processing Systems: A Practical Approach - page 196

a i
b i

c i+1

Half Adder (HA)

HA

p i

a i
b i

s i

s i

g i

c i +1

c i

c i

(a) (b)

a i
b i

p i

a i
b i

0
1
2
3

0

0
1
2
3

s i

Ci+1

g i

1

c i+1

s i

c i

c i

(c) (d)

Figure 5.7 Gate-level design options for a full adder

this design rulewhere DSP48 blocks in the Virtex -4 family of devices are effectively used to gain a

nine times better performance without adding any additional resources compared to a technology-
independent RTL implementation.

5.5.3 Ripple Carry Adder
The emphasis of this text is on high-speed architecture, and an RCA is perceived to be the slowest
adder. This perception can be proven wrong if the design is mapped on an FPGA with embedded
carry chain logic. An RCA takes minimumarea and exhibits a regular structure. The structure is very
desirable especially in the case of an FPGA mapping as the adders fit easily into a 2-dimensional
layout. An RCA can also be pipelined for improved speed.
A ripple adder that adds two N-bit operands requires N full adders. The speed varies linearly with
the word length. The RCA implements the conventional way of adding two numbers. In this
architecture the operands are added bitwise from the least significant bits (LSBs) to the most
significant (MSBs), adding at each stage the carry from the previous stage. Thus the carry-out from
the FA at stage i goes into the FA at stage (i

þ 1), and in this manner carry ripples fromLSB toMSB

(hence the name of ripple carry adder):