Digital Signal Processing Reference
In-Depth Information
8
d[n]
a[n]
b[n]
c[n]
8
+/-
d[n-1]
8
8
8
out[n]
+/-
x
16
e[n]
8
Figure 4.35
Pipelining while maintaining coherency in the datapath
Figure 4.33, a pipeline register needs to be inserted between the multiplier and the subtractor; but,
tomaintain coherency of input e[n] to themultiplier, one register is also added in the path of the input
e[n] to the multiplier.
When some of the feedforward paths of themappedHWdo not meet timings, the designer can add
pipeline registers to these paths. In contrast, there is no simple way of adding pipeline registers in
feedback paths. The designer should mark any feedback paths in the design because these require
special treatment for addition of any pipeline registers. These special transformations are discussed
in Chapter 7.
4.7.3 Selecting Basic Building Blocks
As an example, a dataflow graph representing a signal processing algorithm is given in Figure 4.36(a).
Let there be three different types of multiplier and adder in the library of predesigned basic building
blocks. The relative timing and area of each building block is given in Table 4.1. This example
designs an optimal architecture with minimum area and best timing while mapping the DFG to fully
dedicated architecture.
X[n]
X[n-1]
X[n-2]
X[n-3]
x[n]
x[n-1]
x[n-2]
x[n-3]
x
x
x
x
M1
M1
M3
M3
a1
a2
b1
b2
a
1
a2
b1
b2
+
+
A1
Path
1
Path
2
A2
x
c1
M1
c1
+
A1
Path
2
Path
1
y[n]
y[n]
(a)
(b)
Figure 4.36
One-to-one mathematical operations. (a) Dataflow graph. (b) Fully dedicated architecture
with optimal selection of HW blocks
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