Digital Signal Processing Reference
In-Depth Information
a[n]
d[n]
+
d[n-1]
-
x
out[n]
b[n]
c[n]
e[n]
Figure 4.32
Mapping to a dataflow graph of the set of equations given in the text example
After one-to-one mapping of the DFG to architecture, the design is evaluated to meet the input
data rate of the system. There will be cases where, even after selecting the optimal architectures for
basic operations, the synthesized design does not meet timing requirements. The designer then needs
to employ appropriate mathematical transformations or may add pipeline registers to get better
timing (see later).
Example: Convert the following statements to DFG and then map it to fully dedicated
architecture.
d½¼a½þb½n
ð
4
:
7
Þ
out ½¼dn
ð
½
1
c½n
Þe½n
ð
4
:
8
Þ
This is a very simple set of equations requiring addition, a delay element, a subtraction and a
multiplication. The index n represents the current iteration, and n - 1 represents the result from the
previous iteration. The conversion of these equations to a synchronous DFG is shown in Figure 4.32.
After conversion of an algorithm to DFG, the designer may apply mathematical transformations
like retiming and unfolding to get a DFG that better suits HWmapping. Mapping of the transformed
DFG to architecture is the next task. For an FDA the conversion to an initial architecture is very
trivial, involving only replacement of nodes with appropriate basic HW building blocks.
Figure 4.33 shows the initial architecture mapping of the DFG of (4.7) and (4.8). The operations
of the nodes are mapped to HW building blocks of an adder, subtractor, multiplier and a register.
4.7.2 Pipelining
Mapping of a transformed dataflow graph to fully dedicated architecture is trivial, because each
operation is mapped to its matching hardware operator. In many cases this mapping may consist of
paths with combinational logic that violates timing constraints. It is, therefore, imperative to
break these combinational clouds with registers. Retiming transformation, which is discussed in
Chapter 7, can also be used for effectively moving algorithmic registers in the combinational logic
that violates timing constraints.
8
d[n]
d[n-1]
a[n]
b[n]
c[n]
8
+/-
8
8
8
out[n]
+/-
X
16
8
e[n]
Figure 4.33
DFG to FDA mapping
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