Mapping on Fully Dedicated Architecture - Digital Design of Signal Processing Systems: A Practical Approach - page 159

2 1 3 4

A B C

(a)

B

C

B

A

C

A

B

C

B

(b)

Figure 4.25 SDFG to HSDF conversion. (a) SDFG consisting of three nodes A, B and C. (b) An
equivalent HSDG

is more generic and is suited to modeling several signal processing applications because it provides
flexibility of varying production and consumption rates of each node provided the pattern is repeated
after some finite number of iterations. This representation also works well for designs where a
periodic sequence of functions is mapped on same HW block. Modeling it as CS-DFG, a node, in a
periodic pattern, fires and executes a different function in a sequence and then repeats the sequence
of calls after a fixed number of function calls. Each function observes different production and
consumption rates, so the number of tokens in each firing of a node is different.
Figure 4.27 shows a CS-DFGwhere nodes A, B and C each executes two functions with execution
times of [1, 3], [2, 4] and [3, 7] time units, respectively. In each of their firings the nodes produce and
consume different numbers of tokens. This is shown in the figure on respective edges.
To generalize the execution in a CS-DFG node, in a periodic sequence of calls with period N,
an iteration executes a function out of a sequence of functions f 0 (.), ... f (N -1) . Other nodes also call
functions in a sequence. Each call consumes and produces a different number of tokens.

64

B T
8x8

64 8

C T
8x8

8

8 64 64

8

C i =
1D-DCT(B T (i,:))

F j =
1D-DCT(C T (:,j))

8 3

8 3

Figure 4.26 Computing a two-dimensional DCT in a JPEG algorithm presents a good example to
demonstrate a multi-rate DFG