Digital Signal Processing Reference
In-Depth Information
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Opt DSP
Code
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RTL HDL
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P1
P2
P3
P4
Figure 4.13
Graphical representation of a signal processing algorithm where node P3 is described in
RTL and optimized assembly targeting an FPGA or a particular DSP respectively
x[n-1]
x[n-2]
x[n]
clk
clk
ho
h1
h2
x
x
x
y[n]
+
+
Figure 4.14
Dataflow graph representation of a 3-coefficient FIR filter
a
x
+
V
U
Figure 4.15
Source and destination nodes with a delay element on the joining edge
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