System Design Flow and Fixed-point Arithmetic - Digital Design of Signal Processing Systems: A Practical Approach - page 128

|H(e j ω )| and |H Q (e j ω )|

Freq Response of

∆

h

0 -30

|H(e j ω )|
|H Q (e j ω )|

-10

-40

-20

-30

-50

-40

-50 -60

-60

-70

-70

-80

-80

-90

-100 -90

0 1000 2000 0 500 1000 1500 2000

500 1500

Freq in Hz

Figure 3.32 Change in magnitude of frequency response due to floating-point to fixed-point conversion

specification and then directly design the system in fixed-point format. Optimization techniques
are exploited, but these techniques have yet not found a place in commercial toolboxes primarily
because of their computational complexity. Finding computationally feasible techniques requires
more deliberation and effort from researchers working in areas of signal processing and digital
design.

Exercises
Exercise 3.1

Design a 13-bit floating-point multiplier. The floating-point number has 1, 4 and 8 bits for,
respectively, its sign s, exponential e and mantissa m. Assume a bias value of 7 for the
representation. Use an 8 8-bit unsigned multiplier to multiply two mantissas, and a 4-bit
adder and a subtractor to add the two exponents and then subtract the bias to take the effect of
twice added bias from the addition. Normalize the multiplication and add its effect in the
computed exponential. Draw an RTL diagram and code the design in Verilog. Write a stimulus to
check your design for normalized and denormalized values. Finally, check the design for
multiplication by 1 .

Exercise 3.2

Add the following two floating-point numbers using 32-bit IEEE floating-point format. Show all the
steps in the addition that should help in designing a floating-point adder. The numbers are:

x ¼ 23 : 175

y ¼ 109 : 5661