Digital Signal Processing Reference
In-Depth Information
b 0
w[n]
x[n]
b 0
v[n]
z -1
y[n]
z -1
y[n]
x[n]
z -1
y[n-1]
x[n-1]
b 1
a 1
a 1
b 1
z -1
z -1
x[n-2]
x[n-2]
z -1
a 2
b 2
a N-1
b M-1
z -1
z -1
a N - 1
b N-1
y[n-N]
x[n-M]
a N
b M
z -1
b N
(a)
a N
(b)
b 0
w[n]
y[n]
x[n]
z -1
a 1
b 1
z -1
b 2
a 2
a N-1
b M-1
z -1
b M
a N
(c)
b 0 2
y 2 [n]
b 0 3
b 0 1
w 3 [n]
w 1 [n]
w 2 [n]
y
y 1 [n]
x[n]
z -1
z -1
z -1
a 13
a 11
a 12
b 11
b 12
b 13
z -1
z -1
z -1
a 23
a 2 1
a 22
b 22
b 23
b 21
(d)
Figure 3.24 Equivalent implementation for realizing an Nth-order IIR system. (a) Direct Form-I.
(b) Direct Form-II. (c) Transposed Direct Form II. (d) Cascade formusing DF-II second-order sections.
(e) Parallel form using DF-II second-order sections
 
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