System Design Flow and Fixed-point Arithmetic - Digital Design of Signal Processing Systems: A Practical Approach - page 99

implied decimal

Qn 1. m 1 1 1 1 1 1 0 = Q4.2 = -2+1+0.5 = -0.5

Qn 2. m 2 0 1 1 1 0 1 1 0 = Q4.4 = 1+2+4+025+0.125 = 7.375

Qn . m 0 1 1 0 1 1 1 0 = Q4.4 = 2+4+0.5+0.25+0.125 = 6.875

Figure 3.5 Example of addition in Q format

by 1 removes the redundant sign bit, and the format of the product is changed to Q(n 1 þ n 2 1)

(m 1 þ m 2 þ 1). Below are listed multiplications for all possible operand types.

3.5.4.1 Unsigned by Unsigned

Multiplication of two unsigned numbers in Q2.2 and Q2.2 formats results in a Q4.4 format number,
as shown in Figure 3.6. As both numbers are unsigned, no sign extension of partial products is
required. The partial products are simply added. Each partial product is sequentially generated and
successively shifted by one place to the left.

3.5.4.2 Signed by Unsigned

Multiplication of a signed multiplicand in Q2.2 with an unsignedmultiplier in Q2.2 format results in
a Q4.4 format signed number, as shown in Figure 3.7. As the multiplicand is a signed number, this

1 1 0 1 = 11.01 in Q2.2 = 3.25
1 0 1 1 = 10.11 in Q2.2 = 2.75
1101
1101X
0000XX
1101XXX
1 0 0 0 1 1 1 1= 1000.1111 in Q4.4 i.e.8.9375

Figure 3.6 Multiplication, unsigned by unsigned

1 1 0 1 = 11.01 in Q2.2 = -0.75

0 1 0 1 = 01.01 in Q2.2 = 1.25

1 1 1 1 1 1 0 1 extended sign bits shown in bold

000 0000X
11 1101XX
0 0000XXX
1 1 1 1 0 0 0 1 = 1111.0001 in Q4.4 i.e.-0.9375

Figure 3.7 Multiplication, signed by unsigned