Using a Hardware Description Language - Digital Design of Signal Processing Systems: A Practical Approach - page 79

Exercise 2.8

Draw anRTL diagram for the followingVerilog code. Clearly specify the datawidths of all thewires,
and show multiplexers, registers, reset and clock signals.

module test_module (input [31:0] x0,
input [1:0] sel, input clk,
rst_n, output reg [31:0] y0);
reg [31:0] x1, x2, x3;
reg [31:0] y1;
wire [31:0] out;
assign out = (x0 + x1 + x2 + x3 + y1)>>>2;
always @(posedge clk or negedge rst_n)
begin

always @ (posedge clk or negedge
rst_n) begin
if(!rst_n) begin
y1 < =0;
y0 < =0;

end
else begin
y1 < = y0;
y0 < = out;

if(!rst_n) begin
x1 < =0;
x2 < =0;
x3 < =0;

end

end
endmodule

end
else if (sel==0) begin
x3 < = x2;
x2 < = x1;
x1 < = x0;

end
else if (sel == 01) begin
x3 < = x1;
x2 < = x0;
x1 < = x2;

end
else begin
x3 < = x3;
x2 < = x2;
x1 < = x0;

end

end

Exercise 2.9

Partition the RTL-level design given in Figure 2.25 into two or three modules for better synthesis
result. Write RTLVerilog code for the design. For the combinational cloud, write an empty function
or a task to implement the interfaces.

Exercise 2.10

Design architecture, and implement it in RTLVerilog to realize the following difference equation:

y½n¼x½nx½n 1 þx½n 2 þx½n 3 þ 0 : 5 y½n 1 þ 0 : 25 y½n 2 :

Implement multiplication with 0.5 and 0.25 by shift operations.