Information Technology Reference
In-Depth Information
In summary, the proposed surrogate-IBIS macromodel achieves good accuracy in
the analysis. The macromodels obtained show good accuracy in capturing the
effects of reflections and variations, and their scalability makes flexible design
analysis possible.
4
Surrogate-Based Device Modeling
Scaling of device sizes induced high variability of transistor parameters. There are
two major reasons for this. Firstly, quantum mechanics-based phenomena such as the
drain induced barrier lowering (DIBL) or gate tunnelling which are negligible in long-
channel devices become more significant. Additional physics-based effects in-
creased the dependence of many circuit design quantities including the drain current,
I ds , and device transconductance, g m , on the transistor process parameters such as the
oxide thickness, t ox . Furthermore, the tolerance of semiconductor manufacturing com-
ponents did not scale down as the transistor sizes shrink [16]. As a consequence, the
amount of uncertainty in the design quantities remained constant while device sizes
become smaller leading to higher percentages of variability with respect to the no-
minal values of the transistor process parameters. The experimental data revealed
that the traditional process corner analysis might not reflect the real distribution of the
critical transistor parameters such as the threshold voltage V th [17] while the Monte
Carlo analysis become more computationally intensive with increasing number of
variability factors.
The response surface of design quantities which become more complex with the
presence of extreme process variations can be accurately captured by surrogate mod-
elling. Surrogate modelling aims to express the output quantity in terms of a few input
parameters by evaluating a limited number of samples. These samples are used by the
basis functions which establish the response surface of the desired output. Coeffi-
cients of the basis functions should be optimized to minimize the modelling error.
This approach has been applied to the problem of I ds modelling in order to assess the
effects of variability in analogue circuit building blocks, in particular, the differential
amplifiers [18]. In this section, the modeling of g m of n-channel transistors will be
discussed.
The transconductance g m is an important quantity for analog circuits, particularly in
determining the AC performance of amplifiers, mixers, and voltage controlled oscilla-
tors. The modeling here is based on 65 nm device technology (IBM 10SF design kit)
and uses six process parameters ( t ox , intrinsic threshold voltage V th,0 , intrinsic drain-
source resistance R ds ,0 , intrinsic mobility µ 0 , channel length variation Δ L eff , and chan-
nel doping N ch ) as input to the model in addition to the terminal voltages of the tran-
sistor (gate-source voltage V gs , drain-source voltage V ds , and bulk-source voltage V bs )
and the temperature T . The choice of these process parameters is based on their physi-
cal origin which ensures a weak correlation between each parameter. BSIM model I ds
equations are analytically differentiated to yield g m [19]:
.
g
=∂
I
V
(5)
m
ds
gs
The g m expression is validated by extensive SPICE circuit simulations over the
process corners and at temperature extremes so that it can be used to evaluate the
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