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Fig. 9.
Test setup for model validation
transistor
surrogate
2
Supply
Voltage
3
1.5
2
1
1
0.5
0
0
5
10
15
20
25
30
35
40
50
75
100
125
time (ns)
time (ns)
(a) Case 1 (b) Case 2
Fig. 10.
Output voltage at the far end of the transmission line, (a) Case 1, black solid line—
transistor-model, grey solid line—traditional IBIS, black dash line—proposed surrogate IBIS.
Black dash-dot line—supply voltage. (b) Case 2, grey solid line—transistor, black dashed
line—macromodel.
The accuracy of the macromodels is quantified by computing the timing error and
the maximum relative voltage error. The timing error is defined as the time difference
between the reference and the macromodel voltage responses measured for crossing
half of the output voltage swing. The maximum relative voltage error is defined as
the maximum error between the reference and macromodel voltage responses divided
by the voltage swing.
The results show that in Case 1 when there are large variations of the supply vol-
tage, the surrogate IBIS model has much better accuracy both of the timing error and
of the relative voltage error than the traditional IBIS model. The maximum timing
error of the surrogate-IBIS model is 79 ps, and the maximum relative voltage error is
6.77%. The surrogate IBIS model achieves the improved accuracy by capturing the
complex output capacitance characteristics, the effects of the supply voltage, and gate
modulation effects on the output current [15]. In Case 2, the result shows that the
surrogate-IBIS achieves good accuracy. In this case, the maximum timing error is 70
ps (3.5% of the bit-time) and the maximum relative voltage error is 6.45%. We also
analyze the eye-diagram of the output in Case 2. The eye-width (
W
) was measured
when the eye-height (
H
) was equal to 1 V. The results under different PVT condi-
tions show that the eye-width differences within 0.04 ns (2% of the bit-time).
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