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algorithm [12]. Fig. 8(a) shows the test to obtain the switching output voltage wave-
forms. A simplified circuit to illustrate the 2EQ/2UK algorithm is shown in Fig. 8(b).
The switching output voltage waveforms wfm 1 and wfm 2 were obtained with different
terminal voltage V term , and the unknown coefficients K pu and K pd are derived using the
equations
KtIV
( )
(
( ))
t KtIV
( )
(
( ))
t I
=
0
pu
pu
wfm
pd
pd
wfm
out
1
1
(4)
KtIV
( )
(
( ))
t KtIV
( )
(
( ))
t I
=
0
pu
pu
wfm
pd
pd
wfm
out
2
2
where
I
=−
(
VVR
) /
. I pu and I pd are the output current models.
out
out
term
load
(a) (b)
Fig. 8. (a) Test-benches for extracting model elements output capacitance C gnd and C power (b)
illustration of 2EQ/2UK algorithm.
To implement the new model, we modified the Verilog-A behavioral version of the
IBIS model [13] and applied the surrogate model expressions for the model elements.
The surrogate models were implemented in the form of analog functions.
3.3
Test Results
In this section the surrogate IBIS model is compared to the reference provided by the
transistor-level simulation, and to the traditional IBIS model extracted from SPICE
using the S2IBIS3 v1.0 tool [14].
The test setup is shown in Fig. 9 where the driver is connected to a 0.75-m long
lossy transmission line (RLGC model) with a loading resistor. The characteristic im-
pedance of the transmission line is 50 Ω. The loading resistor is 75 Ω. Two test cases
were examined. The results are shown in Fig. 10.
1. Case 1, used a 250 MHz square wave as a test input signal. The input data has the
pattern “01010” with a 0.1-ns rise/fall time and 2-ns bit-period. The supply voltage
varied from 2.8 to 3.8 V.
2. Case 2, used a data pattern with a 1024 bit long pseudorandom bit sequence
(PRBS) with 2-ns bit time. The power supply voltage was constant.
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