Variation-Aware Circuit Macromodeling and Design Based on Surrogate Models - Simulation and Modeling Methodologies, Technologies and Application - page 249

3.1 Proposed Macromodel Structure

Fig. 5 shows the proposed macromodel structure that is composed of physically-based
equivalent model elements [10]. I pu and I pd represent the nonlinear output current.
Time-variant coefficients K pu and K pd determine the partial turn-on of the pull-
up/down networks during switching transitions. C power and C gnd represent the nonli-
near parasitic capacitance between the output and the supply rails. Surrogate models
of these model elements are constructed, to capture the effects of supply voltage, ter-
minal voltages, semiconductor process, and temperature.

Fig. 5. Structural IO buffer macromodel template with surrogate model elements

3.2 Macromodel Construction

The automatic modeling process described in Section 2 was used to construct surro-
gate models for the model elements in Fig. 5. The method is demonstrated with the
single-ended output buffer circuit shown in Fig. 6. The circuit is designed in 180 nm
CMOS process with a 3.3 V normal supply voltage. The threshold voltage variations
Δ V th in the MOS transistors are considered as the main process variations and they are
assumed to be within ±20% of the nominal value V th0 . The parameter P = Δ V th / V th0 is
used to describe the threshold voltage variation. The supply voltage Vs is assumed to
fluctuate within ±30% of the nominal supply (3.3 V) and temperature ( T ) is set in the
range of 0 to 100°C. In the modeling process, those PVT-related parameters are sam-
pled adaptively in their ranges.
Here modeling data was extracted from transistor-level SPICE circuit simulations.
Fig. 7 (a) shows the circuit test-bench to extract the pull-up output current I pu ( V S , V pu ,
T , Δ V th ). The parameter V pu is defined as the voltage difference between the power
supply rail and the output, and it ranges from V CC to2 V CC covering the maximum
reflection case [11]. Transient simulations were performed and the simulation time
was long enough (in this case it was 1 ms with 1 ns step size) to record a stable output
current I pu .