Variation-Aware Circuit Macromodeling and Design Based on Surrogate Models - Simulation and Modeling Methodologies, Technologies and Application - page 244

Variation-Aware Circuit Macromodeling
and Design Based on Surrogate Models

Ting Zhu, Mustafa Berke Yelten, Michael B. Steer, and Paul D. Franzon

Department of Electrical and Computer Engineering,
North Carolina State University, Raleigh, NC 27695, U.S.A.
{tzhu,mbyelten,mbs,paulf}@ncsu.edu

Abstract. This paper presents surrogate model-based methods to generate
circuit performance models, device models, and high-speed IO buffer
macromodels. Circuit performance models are built with design parameters and
parametric variations, and they can be used for fast and systematic design space
exploration and yield analysis. Surrogate models of the main device characteris-
tics are generated in order to assess the effects of variability in analog circuits.
A new variation-aware IO buffer macromodel is developed by integrating sur-
rogate modeling and a physically-based model structure. The new IO model
provides both good accuracy and scalability for signal integrity analysis.

Keywords: Surrogate Modeling, Macromodel, Variation-Aware, Circuit,
Device Model, Design Exploration, IO Buffer.

1 Introduction

Advances in integrated circuit (IC) technologies have enabled the single-chip
integration of multiple analog and digital functions, resulting in complex mixed-signal
Systems-on-a-Chip (SoCs). However, as the IC technology further scales, process
variations become increasingly critical and lead to large variances in the important
transistor parameters. As a result, circuit performance varies significantly, and some
circuits may even fail to work. The large process uncertainties have caused significant
performance yield loss. In addition, reliability issues and environmental variations
(such as supply voltage and temperature) contribute to further yield reduction and
make it more challenging to create a reliable, robust design. In handling this prob-
lem, it is important to consider the effects of variations in circuit modeling and design
analysis at an early stage. However, this is a nontrivial task. In this paper, we apply
surrogate modeling to handle the complexities in variation-aware circuit macromode-
ling, design analysis, and device modeling. We demonstrate the benefits of using
surrogate modeling in enhancing the accuracy, flexibility, and efficiency in those
applications.

2 Circuit Performance Macromodeling with Variations

2.1 Overview of the Method

Circuit designers are confronted with large design spaces and many design variables
whose relationships need to be analyzed. In this situation, tasks such as sensitivity