Digital Signal Processing Reference
In-Depth Information
R
0
= 1Ω
+
+
V
A
1
(
S
)
V
A
2
(
S
)
Z
(
S
)
−
−
FIGURE10.
VoltageDividerCircuitfor
G
(
S
)
L
2
L
3
L
M
C
1
L
1
C
2
C
3
C
M
FIGURE11.
Realizationof Impedance
Z
(
S
)
Finally,
Z
(
S
)
represents realizable reactances (consisting of capacitors and inductors only) and can
be decomposed into its Foster II canonical form, as in Fig.
11
, in accordance with
1
Y
(
S
)
Z
(
S
) =
(27)
M
I
=2
1
SL
1
+
SC
I
S
2
C
I
L
I
+
1
Y
(
S
) =
SC
1
+
(28)
where
M
=
N
/2
for even
N
and
M
= (
N
+
1
)
/2
for odd
N
, and where
C
I
represent capacitances
and
L
I
represent inductances (for
I
=
1, 2, . . . ,
M
), and inductor
L
1
is only present for even
N
.
•
The impedance
Z
(
S
)
in Fig.
11
is substituted into Fig.
10
and the precompensation is applied to the
resulting network. This amounts to a modification of circuit elements in accordance with:
V
A
1
(
S
)
1
−
ST
/2
V
′
A
1
(
S
) =
(29)
The resistance in
R
0
in Fig.
10
is modified to:
R
′
0
=
Z
2
R
0
(30)
