Digital Signal Processing Reference
In-Depth Information
[50]
O. Gustafsson and A. G. Dempster. On the use of multiple constant multiplication
in polyphase fir filters and filter banks.
In
Proc. Nordic Signal Processing Symp.
, pages
53-56, Espoo, Finland, June 9-11, 2004.
[51]
O. Gustafsson and H. Johansson. Efficient implementation of FIR filter based rational
sampling rate converters using constant matrix multiplication. In
Proc. Fortieth Asilomar
Conf. Signals, Systems and Computers ACSSC '06
, pages 888-891, 2006.
[52]
A. G. Dempster, O. Gustafsson, and J. O. Coleman.
Towards an algorithm for matrix
multiplier blocks.
In
Proc. European Conf. Circuit Theory Design
, Krakow, Poland, Sept.
1-4, 2003.
[53]
M. D. Macleod and A. G. Dempster. A common subexpression elimination algorithm
for
low-cost
multiplierless
implementation
of
matrix
multipliers.
Electronics Lett.
,
40(11):651-652, May 2004.
[54]
N.
Boullis
and
A.
Tisserand.
Some
optimizations
of
hardware
multiplication
by
constant matrices.
IEEE Trans. Computers
, 54(10):1271-1282, Oct. 2005.
[55]
L. Aksoy, E. Costa, P. Flores, and J. Monteiro. Optimization algorithms for the
multiplierless realization of linear transforms.
ACM Trans. Design Automation Electronic
Syst.
, vol. 17, no. 1, article 3, Jan. 2012.
[56]
A.
G.
Dempster
and
N.
P.
Murphy.
Efficient
interpolators
and
filter
banks
using
multiplier blocks.
IEEE Trans. Signal Processing
, 48(1):257-261, Jan. 2000.
[57]
M. Abbas, O. Gustafsson, and H. Johansson. On the fixed-point implementation of
fractional-delay filters based on the farrow structure.
IEEE Trans. Circuits Syst I: Regular
Papers
, 2012. to appear.
[58]
O. Gustafsson. Lower bounds for constant multiplication problems.
IEEE Trans. Circuits
Syst. II
, 54(11):974-978, Nov. 2007.
