Major Areas of Opportunity - Implications of Emerging Micro-and Nanotechnologies - page 34

Latchup occurs when an ionizing trail creates a high-conductivity path be-
tween a current source and a current sink, generating a temporary electric short.
Latchups are minimized by adding guard bands to transistors and by using sili-
con-on-insulator designs. The latter approach is used in fabricating radiation-
hardened electronics for space applications. If latchup occurs, it may be corrected
by momentarily removing power to the affected circuit. Latchup conditions are
detected by monitoring power consumption to individual chips, or by adding
“watchdog” timers.
Table 3-1 gives approximate radiation hardness levels for different types of
semiconductor devices that were available in 1990. The actual radiation tolerance
varies widely from design to design and is also fabrication-process-dependent, so
radiation testing should be performed on selected components. Transistor-tran-
sistor logic (TTL) and emitter-coupled logic (ECL) circuits are inherently more
radiation hard than CMOS, but they require more power. Metal-oxide (n-type)
silicon (NMOS), metal-oxide (p-type) silicon (PMOS), current-current logic (I 2 L),
and silicon-on-insulator metal oxide semiconductor (MOS) circuits can be fully
immune to latchup. CMOS circuitry fabricated onto silicon-on-insulator sub-
strates has traditionally provided radiation-tolerant electronics for space applica-
tions. The use of thin silicon over an insulator reduces the volume for charge
collection along an ionizing particle track, thus reducing the amount of charge
introduced into individual gates. Thin-film silicon-on-insulator (TFSOI) technol-
ogy is now being considered for commercial electronics because it can provide
enhanced low-voltage operation, simplified circuit fabrication, and reduced cir-
cuit sizes relative to bulk silicon counterparts. 42 TFSOI would be particularly

TABLE 3-1 Approximate Radiation Hardness Levels for Semiconductor Devices

Technology Total Dose (rads) (silicon)

10 3 -10 4

CMOS (soft)

5 × 10 4 -10 6

CMOS (hardened)

10 3 -10 4

CMOS (silicon-on-sapphire: soft)

>10 5

CMOS (silicon-on-sapphire: hardened)

10 7

ECL

I 2 L 10 5 -4 × 10 6

5 × 10 3 -10 7

Linear integrated circuits

10 3 -10 5

MNOS

5 × 10 5 -10 6

MNOS (hardened)

7 × 10 2 -7 × 10 3

NMOS

4 × 10 3 -10 5

PMOS

>10 6

TTL/STTL

SOURCE: Adapted from Griffin, M.D., and J.R. French. 1991. Space Vehicle Design. Washington,
D.C.: American Institute of Aeronautics and Astronautics.