Hardware Reference
In-Depth Information
Thus, in order to check if the line is in cache or not it is enough to check the "hit"
bit.
if (line_124.hit == 0)
insert_line(&line_124);
This code is executed every time a basic block ends. The method used to model a
cache miss, insert_line() , takes the address of the miss line and allocates it in
cache. The allocation algorithm works as follows: the address of the line is used to
find the target index. If there are free locations for this index, the address is simply
recorded in the line pointers array and the hit flag of the line is set to true. If the
index lines are full, the victim selection algorithm selects the victim line that must
be expelled. The hit flag of the victim line is set to false through its pointer, and its
location in cache is replaced by the new one. This way, the next time the victim line
is required, the hit field will be false.
insert_line(icache_line *line) {
icache_line *victim;
victim = get_victim_line(line->set);
if (victim != NULL) victim->hit = 0;
line -> hit = 1;
victim = line;
}
As a consequence of the entire process, tag searches are eliminated, and the cache is
accessed only at misses, which is a small percentage of all the cache accesses. Thus,
the cache modeling overhead is minimized. For data caches the solution applied is
similar.
Note that no real caching of data is performed in our model during execution. As
the SW code is executed natively, its execution does not depend on the behavior of
the associated cache in the HW platform. Our cache modeling technique only models
performance effects, not the actual HW behavior. This makes the technique faster
than other cache simulation approaches.
2.3.2
RTOS Modeling
One of the most important points when transforming a high-level description into a
real SW implementation is the inclusion of the OS. The SW code is gradually refined,
mapping high-level facilities, such as communication and synchronization facilities,
to the target OS facilities. Thus, the development infrastructure has to support the
refined SW code, providing the target OS facilities inside the timed TLM model of
the application SW.
The OS model included in M3-SCoPE is divided in a similar way to real OSs.
An OS can be divided into several layers [ 59 ]. In the upper part, we can find the
system call handlers that support the API. In the middle, the layers for internal OS
management form what can be called the kernel core. At the lower level, there are
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