M3-SCoPE: Performance Modeling of Multi-Processor Embedded Systems for Fast Design Space Exploration - Multi-objective Design Space Exploration of Multiprocessor SoC Architectures - page 27

Fig. 2.4 XML description
with configurable number of
processors. Depending on the
parameter “CPUS”, defined
for each simulation by the
DSE tool, the system model is
created. Task allocation is
modified depending on the
number of processors

Fig. 2.5 XML description
with configurable HW
architectures. The figure
shows a two possible
configurations for as an
interconnection component: a
bus or a Network-on-Chip
(NoC)

2.2.1.3 Selecting Complete Configurations

The third configuration option provided is to define several complete configurations
and select one on each simulation. For example, in Fig. 2.5 , two different HW archi-
tectures are described ( "arch1" and "arch2" ). The one selected for each simulation
is defined in the "Implementation" clause. In this example, the architecture selected
depends on the "ARCH" identifier. Its value must be set in the System Configuration
file to "arch1" or to "arch2" .
The system description mechanism allows dividing the system description in
parts and exploring different combinations. Multiple HW component lists, HW
architectures or SW allocations can be described to be explored by the DSE tool.