Hardware Reference
In-Depth Information
Design Space Exploration requires auxiliary tools to provide the exploration en-
gines with the metrics needed to evaluate the different system configurations. For
evaluating complex HW/SW MPSoC systems [ 30 ], very flexible evaluation mecha-
nisms are required. Static mechanisms are adequate to evaluate the effect of different
parameter values in well known architectures. The analysis of internal processor
components or cache configurations are examples in that context. However, to eval-
uate unknown or very flexible architectures, analysis methods based on mathematical
equations are not applicable. Evaluation mechanisms based on simulation are then
selected.
Simulation environments for DSE have to overcome several challenges. Mainly,
these simulations require very fast speeds, considering the large amount of points
to be simulated. Thus, modeling techniques need to evaluate all the configurations
selected by the DSE tools without provoking additional delays. While HW simulation
can be performed at different abstraction levels using appropriate languages such as
VHDL, Verilog, System-Verilog and SystemC [ 58 ], efficient and sufficiently accurate
SW simulation requires additional efforts. Electronic System Level (ESL) [ 4 ] has
been proposed as an adequate abstraction level for complete system simulations
[ 38 ]. At this level, there are three main methodologies used for SW simulation:
Instruction-Set Simulation (ISS), virtualization with binary translation and native
co-simulation.
The first solution, ISS-based HW/SW co-simulation, is the main industrial plat-
form simulation technology supported by mature commercial tools offered by all the
major vendors [ 40 , 56 ]. Currently available commercial modeling and simulation
tools are based on previous research activity in academia. In [ 7 ] a generic design
environment for multiprocessor system modeling was proposed. The environment
enables transparent integration of ISSs and prototyping boards. As an evolution of
this work, in [ 8 ] a SystemC infrastructure was developed to model architectures with
multiple ARM cores. This approach provides a set of tools that enables designers to
efficiently design SW applications (OS ports, compilers, etc.). A fully operational
Linux version for embedded systems was ported on the platform. Software simu-
lation was based on an ISS for each processor, thus presenting the advantages and
disadvantages commented above. Moreover, it cannot be easily used to evaluate
platforms that do not contain ARM processors.
Several approaches have been proposed to improve the state-of-the-art of com-
mercial tools (Fig. 2.1 ). One of them is the modification of the OS running over the
ISS. As the OS is in fact the interface between SW applications and the rest of the
system, it can be used to save simulation time. In [ 62 ], a technique based on virtual
synchronization is presented to speed up execution of several SW tasks in the ISS.
Only the application tasks run over the ISS. The OS is modeled in the co-simulation
back-plane thus accelerating its simulation. As the OS execution time is only part of
the total execution time, the gain is limited.
A recent technology proposed for SW simulation is using virtualization with
binary translation. The most representative virtualization technology is QEMU [ 54 ].
SW emulation is based on virtualization. The binary code of the target processor is
dynamically translated to the host executing the same functionality. In its original
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