Hardware Reference
In-Depth Information
however the general procedure to the specificities of its particular application and
context, but without modifying the aim and the general steps described above.
1.5
Conclusions
In this chapter, the main structure of the MULTICUBE design flow has been intro-
duced to be detailed in the next chapters. The founding principles of the proposed
structure are meant to cover the gap between the system-level specification and the
definition of the optimal application-specific architecture. The flow is based on the in-
teraction of two frameworks to be used at design time: the Design Space Exploration
Framework, an architecture exploration set of tools, and the Power/Performance
Estimation Framework, a set of modeling and simulation tools operating at several
levels of abstraction. The DSE flow also includes a Run-time Resource Manager
able to select at run-time the best design alternatives in terms of power/performance
trade-offs generated during the design-time exploration phase.
References
1. Avasare, P., Vanmeerbeeck, G., Kavka, C., Mariani, G.: Practical approach to design space
explorations using simulators at multiple abstraction levels. In: Design Automation Conference
(DAC) User Track Sessions. Anaheim, USA (2010)
2. Bishop, C.: Neural Networks for Pattern Recognition. Oxford University Press (2002)
3. Joseph, P., Vaswani, K., Thazhuthaveetil, M.: Construction and use of linear regression mod-
els for processor performance analysis. High-Performance Computer Architecture, 2006. The
Twelfth International Symposium on pp. 99-108 (2006)
4. Joseph, P.J., Vaswani, K., Thazhuthaveetil, M.J.: A predictive performance model for super-
scalar processors. In: MICRO 39: Proceedings of the 39th Annual IEEE/ACM International
Symposium on Microarchitecture, pp. 161-170. IEEE Computer Society, Washington, DC,
USA (2006). DOI http://dx.doi.org/10.1109/MICRO.2006.6
5. Lee, B.C., Brooks, D.M.: Accurate and efficient regression modeling for microarchitectural
performance and power prediction. Proceedings of the 12th international conference on Archi-
tectural support for programming languages and operating systems 40 (5), 185-194 (2006). DOI
http://doi.acm.org/10.1145/1168917.1168881
6. Mei, B., Sutter, B., Aa, T., Wouters, M., Kanstein, A., Dupont, S.: Implementation of a coarse-
grained reconfigurable media processor for avc decoder. J. Signal Process. Syst. 51 (3), 225-243
(2008). DOI http://dx.doi.org/10.1007/s11265-007-0152-8
7. Posadas, H., Castillo, J., Quijano, D., Fernandez, V., Villar, E., Martinez, M.: SystemC plat-
form modeling for behavioral simulation and performance estimation of embedded systems.
Behavioral Modeling for Embedded Systems and Technologies: Applications for Design and
Implementation pp. 219-243 (2010)
Search WWH ::




Custom Search