Hardware Reference
In-Depth Information
contain the IMEC proprietary ADRES VLIW processor and its scratch-pad local
data (L1) memory. The processing nodes are connected to the memory nodes by
a configurable communication infrastructure. It can be either a multi-layer AHB
bus, which provides a full point-to-point connectivity, or a NoC model built with
the CoWare AVF cross-connect IP.
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A High-Level time-annotated Simulator (HLSim, developed by IMEC) that pro-
vides a fast simulator of the ADRES platform at higher abstraction level to
estimate metrics like performance and power consumption for a given plat-
form architecture executing a parallelized version of the application. During the
MULTICUBE project, HLSim has been extended with metrics on energy con-
sumption derived from a multimedia use case for a relative comparison between
different architectures and parallelizations. The introduction of HLSim in the de-
sign flow has provided several benefits such as speeding up the simulation and
starting up the design exploration earlier than planned. HLSim-based explorations
are much faster than TLM-based ones so as more extensive DSE was done by using
HLSim to extract Pareto set information to be used at run-time.
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An instruction set simulator has been used for SP2 superscalar processor provided
by STMicroelectronics and one simulator for the many-core architecture provided
by ICT Chinese Academy of Science. Both simulators expose program execution
time and power consumption as system-level metrics. More in detail, the ICT
many-core architecture is a tiled MIMD machine composed of a bi-dimensional
grid of homogeneous, general-purpose compute elements, called tiles . A 2D-mesh
network architecture is used for connecting the cores to a non-shared memory
sub-system.
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The DS2's STORM platform, a control-oriented architecture for powerline
communication. The platform is used to model a PLC (Programmable Logic
Controller) technology with several implementation choices. For this platform,
both Ethernet QoS and internal communication are considered as metrics.
Given these target simulators, the MULTICUBE project developed a methodology,
the multi-simulator based DSE approach shown in Fig. 1.2 , to avoid potentially sub-
optimal DSE results and to speed up the DSE process by exploiting multiple platform
simulators to run the application at different abstraction levels.
The main idea is to get timing information (in terms of processor cycles) for
an application execution on an accurate simulator (e.g. TLM-based cycle-accurate
simulator) and feed this timing information back to a high-level timed simulator (e.g.
HLSim) to achieve validation across simulators. Then, the DSE is done with a large
number of application runs by using faster higher-level simulators (e.g. HLSim) and
then the derived interesting operating points (usually clusters of operating points) are
refined by using more accurate simulators (e.g. TLM-based and/or cycle-accurate
simulators). The proposed methodology exploiting the synergy of multiple simulators
at several abstraction level can be used to further speed up the DSE process while
guaranteeing good accuracy of the simulation results. The methodology has been vali-
dated for the MPEG4 encoder application provided by IMEC by using three different
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