Design Space Exploration for Run-Time Management of a Reconfigurable System for Video Streaming - Multi-objective Design Space Exploration of Multiprocessor SoC Architectures - page 196

The RRM can trade-off frame rate and power consumption of the multiple MPEG4
by acting on two parameters: the parallelizations of the MPEG4 instances and the fre-
quencies of the ADRES cores. In this sense the operating frequency of each ADRES
core can be dynamically modified independently by adopting Dynamic Voltage and
Frequency Scaling (DVFS) techniques. In particular the frequency range for the
ADRES cores is = {20, 60, 100, 140, 180, 220} MHz, while the StrongARM is
operating at 206 MHz.

9.3.1 Simulation Tool-Chain

For evaluating performance values of the MPSoC platform, a multi-simulator frame-
work has been used [ 1 ]. More specifically, a Transaction-Level Model simulator
(TLMsim) built with CoWare platform design tools enables the cycle-accurate anal-
ysis of the multi ADRES system and the underlying communication infrastructure.
This cycle-accurate simulator is too slow for enabling the analysis of many oper-
ating configurations for the MPEG4 encoder application. To cope with this problem
a High Level Simulator (HLSim) has been used.
HLSim exploits back-annotated information of execution time derived from the
cycle-accurate simulator. Execution time figures for all the kernels are recorded
during cycle-accurate simulations and are fed back into HLSim as input while running
the application.
In practice, during a first recording phase, the sequential version of the application
is simulated on the cycle-accurate simulator; application kernels are profiled and
performance indices (e.g. processor execution cycles) are saved into a database.
Then, HLSim uses this profiled data library during its application simulation to
derive accurate timing for application execution. HLSim does timed simulation of
the application meaning that HLSim keeps track of local time in each thread and this
time is appropriately adjusted during thread synchronizations. Performance indices
are also scaled to the frequencies of the processors where kernels are executed.
Given an application version and the frequency of each thread, the timing feedback
mechanism let HLSim to provide a very fast but approximate evaluation of the
platform performance indices.
Comparing HLSim with the cycle accurate TLMsim on simulating the MPEG4
encoding of 10 frames in 4CIF resolution, we obtain that HLSim has an execution
time of 45 s with respect to TLMsim which requires 4 h. This simulation time saving
is obtained at the cost of the simulation accuracy, in fact HLSim has a simulation
error that is always lower than 20%.
The availability of HLSim enables the design-time DSE phase to quickly investi-
gate many frequency combinations for each application version. The results obtained
by HLSim for some simulations are then validated with the cycle accurate simulator.
Cycle-accurate simulator can also be used for DSE phase but within a small focused
interesting region obtained from HLSim-based DSE phase. This strategy of using
two simulators enables application designers to evaluate DSE phase efficiently [ 1 ].