Hardware Reference
In-Depth Information
via validation on the cycle accurate simulator. This allows to speed up the exploration
without reducing the quality of the final results.
The Chapter is organized as follows. In Sect. 9.2 we present the use case scenario
introducing the MPEG4 application and its different parallel versions. Then, Sect.
9.3 gives an insight of the target MPSoC platform and the simulators used during
the design-time DSE. Section 9.4 reports the results obtained from the proposed
methodology during the design-time DSE phase first (Sect. 9.4.1 ) and, second, from
the RRM during the run-time execution (Sect. 9.4.2 ). The Chapter finally concludes
in Sect. 9.5 summarizing the most relevant results.
9.2
Case Study
The case study presented in this Chapter concerns the management of system
resources for a multiple-stream MPEG4 encoding chip dedicated to automotive cog-
nitive safety tasks. In particular we are targeting an MPEG4 encoding for a 4CIF
video resolution. The application code is specifically optimized for compilation on
the target MPSoC system in which the main computational element is the coarse-grain
reconfigurable ADRES processor [ 5 ].
9.2.1
Application Description
The MPEG4 encoder is an industry-standard, block-based, hybrid video encoder.
The structure of the MPEG4 encoder is shown in Fig. 9.1 and details can be found
in [ 7 ]. Mainly the MPEG4 encoder is composed of the following functional blocks:
￿
Motion Estimation (ME) compares the current frame with a reference frame
previously processed in order to estimate the motion within the frames.
￿
Motion Compensation (MC) compensates the estimated motion in the goal of
increasing the efficiency of the compression.
+
Current
Frame
Tex t u r e
Coding
-
Motion
Estimation
Reference
Frame
Motion
Comp.
+
Entropy
Coding
Bitstream
Packetizing
Reconstr.
Frame
Tex t u r e
Update
+
Fig. 9.1 Overview of the MPEG4 encoder application
 
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