Design Space Exploration of Parallel Architectures - Multi-objective Design Space Exploration of Multiprocessor SoC Architectures - page 183

Instruction queue

Register file

1
1
1
1
0
0
0

3

Functional Unit 5

4

5

2

D cache

0
0
Full / Empty

I cache

5

1

L2 cache

Fig. 8.8 The ICT Cycle-Accurate Simulator

8.3.4 Design Space and Application

One goal of the design of Transformer is to make a reconfigurable platform, allowing
further tuning as the evaluation works goes on. According to the system metrics, the
designers can tune the hardware arguments for higher performance. In the simulator,
all the tunable arguments are collected in a configuration file in XML style. When
the simulator is started, it reads the arguments from this configuration file. The
design space, which is shown in Table 8.4, is composed of 1,134 design points.
As an additional rule in the design space, the associativity of the level-2 cache
should be greater than the sum of the associativities of the level 1 instruction and

Table 8.4 Parameter space
for the ICT many-core
platform

Parameter Minimum Maximum

Mesh_order 2 8

Cache_block_size 32 64

ICache_ways 2 16

Icache_entries 128 512

DCache_ways 2 16

DCache_entries 128 512

L2Cache_ways 4 32

L2Cache_entries 128 512

L2Cache_access_latency 3 10

Memory_size 8 32

Memory_access_latency 30 100

Router_buffer_entries 2 8