Design Space Exploration of Parallel Architectures - Multi-objective Design Space Exploration of Multiprocessor SoC Architectures - page 173

￿ Configurable out-of-order parameters: renaming register number, instruction

issue window width, reorder buffer depth, etc

￿ Configurable cache parameters: cache size

￿ Runtime resizable secondary cache

The experiments presented in this section were performed using Sp2sim, a regis-
ter transfer level cycle accurate simulator, which runs its applications according to
SP2's pipelines and configurations. Sp2sim models precisely the SP2 microproces-
sor design, which includes both the MIPSISA32r2 ISA and PRA [ 5 ]. It also embeds
a model of external memory controller, which can be configured to measure the
performance for different memory latencies and sizes. The interface between the
processor model and the memory controller model is a 64-bit AXI interface. Sp2sim
implements both an area and power consumption estimation algorithms. Sp2sim is
written in C++ language so as to achieve high simulation speed. It runs on Linux
x86 or x86_64 platforms.

8.2.2 Design Space and Application

The SP2 implementation provides eleven configurable parameters, which are clas-
sified into three categories: out-of-order execution engine, cache system and branch
prediction. By adjusting these parameters, the user can get different processor im-
plementations targeting to distinct application areas. The list of parameters together
with a description and their possible values is presented in Table 8.1 .
The SP2 simulator produces seven system metrics, which are grouped in three
categories: performance, power dissipation and area occupation. Table 8.2 describes
the system metrics.
The selected application for the experiments presented in this section is gzip ,a
popular data compression program written by Jean-Loup Gailly, which comes from
SPEC CPU2000 benchmark suite [ 8 ]. It has been selected since its size is relatively
small, and the program behavior is more regular than many other applications.

Table 8.1 The eleven configuration parameters
Category Parameter Description Values

Out of order execution rob_depth Reorder buffer depth 32, 48, 64, 80, 96, 112, 128

rmreg_cnt Rename register number 16, 32, 48, 64

iw_width Instruction window width 4, 8, 16, 24, 32

Cache system icache_size Instruction cache size 16, 32, 64

dcache_size Data cache size 16, 32, 64

scache_size Secondary cache size 0, 256, 512, 1024

lq_size Load queue size 16, 24, 32

sq_size Store queue size 16, 24, 32

msh_size Miss holding register size 4, 8

Branch prediction bht_size Branch history table size 512, 1024, 2048, 4096

btb_size Branch target buffer size 16, 32, 64, 128