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development of an Open Source tool and to the re-targeting of a proprietary state-
of-the-art multi-disciplinary optimization tool that can be directly applied today to
embedded systems design. One of these tools is M3Explorer [
6
], an open source tool
developed from scratch in the MULTICUBE project, and the other is modeFRON-
TIER™ [
2
], an already existing proprietary tool widely used in multidisciplinary
optimization, which has been re-targeted to the domain of embedded systems.
This chapter presents two case studies of design space exploration in embedded
systems to illustrate the benefits of the use of automatic tools from an industrial
perspective. Section
8.2
describes a design space exploration study performed on
a low power processor design and Sect.
8.3
describes the application of response
surface models on a many-core architecture design.
8.2
Design Case Study: Design Space Exploration of the STM
Industrial SP2 Platform
This section describes the application of automatic design space exploration for the
design of a low-power processor developed by STMicroelectronics, using the mode-
FRONTIER multidisciplinary optimization tool. The objective is to demonstrate the
benefits of the introduction of an automatic design process not only by considering
the final objective quality, but also its effects on the entire design process within
the corporate. The experiment is an extension of the benchmark used in Chap. 3 to
analyze the behavior of the optimization algorithms proposed in the MULTICUBE
project [
7
].
8.2.1
Architectural Model Description
The SP2 processor from STMicroelectronics is a low power and high performance
microprocessor offering comparable performance to entry-level desktop micropro-
cessors. It is designed for both generic and mobile applications that need low power
dissipation and high peak performance. The presence of a SIMD coprocessor makes
it suitable for multimedia applications.
The main architectural features of the SP2 processor can be summarized as
follows:
MIPSISA32 release2 compatible instruction set architecture (ISA) and privilege
resource architecture (PRA)
4-issue superscalar out-of-order execution
Built-in 2 integer ALUs, 2 interleaved load-store units
Split primary instruction and data cache
64-byte cache line, 4-way set associative primary caches
64-byte cache line, 8-way set associative unified exclusive secondary cache
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