High-Level Modeling and Exploration of a Powerline Communication Network Based on System-on-Chip - Multi-objective Design Space Exploration of Multiprocessor SoC Architectures - page 167

40000000.0

Real

30000000.0

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Regression Line

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MAX_CELLS_FEC_value

Fig. 7.15 MAX_CELLS_FEC vs Throughput, from Node 0 to Node 1

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MAX_CELLS_PKT_value