High-Level Modeling and Exploration of a Powerline Communication Network Based on System-on-Chip - Multi-objective Design Space Exploration of Multiprocessor SoC Architectures - page 166

to note that this result that we have found in a theoretical approach has also been
tested on real powerline systems in field trials.

7.2.3.2 Find the Optimum Point for the Design Parameters

Once the correctness of the design has been verified using MULTICUBE proce-
dure, we can proceed to analyze the different results obtained through the automatic
simulations in order to find the correct optimum point for the design parameters
under study. As we mentioned at the beginning of this study, the objective is to
find the correct point where latency is minimized (the transmission of a UDP flow
takes minimum time), memory is minimized (since memory is expensive in an em-
bedded system) and throughput is maintained (no application data loss). In order
to achieve this ambitious objective, we will go through the database provided by
modeFRONTIER and analyze the different figures (Figs. 7.14 - 7.16 ).

284246.9

264246.9

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Real
Feasible
Unfeasible
Error

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164246.9

Virtual

144246.9

Feasible
Unfeasible

124246.9

Error

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Regression Line

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64 1064 2064 3064 4064

MAX_CELLS_FEC_value

Fig. 7.14 MAX_CELLS_FEC vs Mean Latency, from Node 0 to Node 1