Hardware Reference
In-Depth Information
Table 7.2
Actors participating to virtual platform analysis
Actor
Use
Goal
SW designers
Develop application Software over the
virtual platform instead of waiting for
the FPGA prototype or the ASIC
design
Speed up design process
HW designers
Fine tune the hardware sub-system and
the interactions between the hardware
and the software. Proceed with the
refinement process
Optimize HW blocks and the interface
between HW and SW
System
designers
Explore architectural approaches and
freeze design parameters
Obtain the optimum design and
architecture
reuse of the different components, increase the flexibility of the platform and to
speed-up the learning-curve of the model.
All the communication interfaces of the components of the model are described
in high level SystemC using TLM libraries
All the behavior of the components of the model are described in plain C code in
order to facilitate HW/SW partitioning
TLM libraries have been tuned by DS2 in order to monitor transactions, facilitate
the reuse of modules and reduce the learning curve of the model
The platform has been designed to be highly configurable and in order to reuse
as many blocks as possible
In order to stress as many parameters as possible and to cope with all possible
situations, the current version of the platform is highly configurable by itself through
the use of proprietary ASCII configuration files that can modify the behavior of
the main components of the system, independently of their hardware or software
nature. In MULTICUBE flow, some of these parameters are overwritten directly by
MULTICUBE configuration files in order to automatically control the optimization
process. In the use case, and in order to make comparisons possible, we have modified
the platform to run either in stand-alone mode (using only ASCII configuration files
as input) or in MULTICUBE mode using the project configuration files in addition
to the ASCII configuration files.
STORM platform has been designed with the objective to be as general, flexible
and open as possible and do not rely on commercial tools for running. In this sense,
SystemC and TLM were chosen as the backbone of the platform but, thanks to the
flexibility of the platform, other languages (VHDL, Verilog, SystemVerilog, C, C++,
SCV, etc.) can be added when needed to investigate particular aspects of the flow or
different abstraction levels.
For the purposes of MULTICUBE project, we will focus on the system level for
optimizing the system parameters of the platform. This way, only SystemC-TLM
components have been considered and no RTL code has been included. How-
ever, it is interesting to mention that the whole process can be also run over other
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