Hardware Reference
In-Depth Information
since all the peripheral configurations must be recovered from main memory, and
sometime this is possible only after a proper cold-start device initialization procedure.
Hibernation is the more effective saving state: power consumption minimization is
at its optimal value, saving the system configuration in a persistent storage and pow-
ering off all devices (memory included in some cases). Unfortunately, as one can
argue, this last state is also the most expensive in terms of recovery time. A complete
system restart is generally required, and it is done during the boot-up procedure in
order to keep dynamic overhead at a minimum.
The main challenge for a successful implementation is the proper tracking of de-
vice functional dependencies. Different devices in a system could be interconnected
to form subsystems. For instance a USB device, such as a memory stick, is connected
to the port of an HUB which in turn connects to a port of a USB host controller. All
this chain define a USB subsystem. Finally the host controlled could be either a sys-
tem device or a gateway towards a PCI bus; which in turn defines another subsystem.
Considering all the devices within a system and their inter-dependencies with respect
to their functional dependencies what we get is logical dependency tree rooted at the
CPU and having a device at each end node. This tree specifies an implicit order that
must be respected both on suspend, starting the suspension from nodes and visiting
the tree up to the root, and on resume, by converse visiting it starting from the root
node down to the device nodes.
Clock Framework
The Clock Framework has been introduced in the Linux kernel to optimize the dy-
namic power consumption associated to the clock distribution tree. The proposed
framework is based on the management of the system clock signal. The hierarchical
generation and distribution of the clock signal opens several opportunities for engi-
neers to reduce power. The effective validity of the approach is driven by the fan-out
value and the switching activity of the clock signal.
Purpose of the framework is to export the programmability of such components
to the software level [ 26 ]. In this way, it is possible to cut-off some tree edges
according to the desired computational activity; this is actively done by switching
off a selected subset of LDO, PLLs or DIV modules. The approach takes even more
advantage in some partitioned systems, in which several independent subsystems
receive the clock from a common source, the top-level system clock, and scale the
input signal according to local optimization policies, using DIV modules. In this
way, individual operating requirements can be locally addressed with little silicon
cost.
There are two main mechanisms for clock management: clock stopping and clock
scaling . The former technique allows to disconnect the clock line from the associated
PLL, and to eventually power off the PLL. Such mechanism gates the clock to the
entire sub-tree controlled by the actual PLL that has been turned off. Clock scaling,
on the other hand, does not disable clocks, but it instead scales down the incoming
signal using physical dividers or reprogramming the top PLL for the current sub-tree.
Search WWH ::




Custom Search