Design Space Exploration Supporting Run-Time Resource Management - Multi-objective Design Space Exploration of Multiprocessor SoC Architectures - page 98

Fig. 5.1 Exploration
tool-flow for Run-time
Resource Management

Application designer

Design-time
design space
exploration

MP-SoC
platform
simulator

Application
configurations

At design time

At run time

Run-time Resource
Manager
(RRM)

desired output parameters (in our case execution time and power consumption)
while meeting output constraints (in our case throughput QoS).
For each application, a multi-dimension Pareto set of optimal configurations is
identified at design time, by analyzing and exploring several parallelizations and im-
pacts on the constraints, the platform resource usage, and the costs. This is automated
through a Design Space Exploration tool coupled with a platform simulator(s):
￿ The used design space explorers can be: either modeFRONTIER commercially

available, or Multicube Explorer [ 41 ] (being open-source, and being the target
of this Chapter). Typically in design space exploration for multi-core systems,
the number of possible application configurations can be huge. Hence these ex-
ploration tools with sophisticated analytical and modeling techniques are needed
within the embedded system design cycle. And as previously mentioned, they
also allow alleviating the run-time decision making.

￿ As pointed in [ 13 ], platform simulations can be done at many abstraction lev-

els: e.g. functional-level simulation, timed simulation, cycle-accurate simulation.
But the key problem is the following one: the more accurate the simulator, the
more time it takes to perform a simulation. Hence from the Design-Space Ex-
ploration point of view, which needs a large number of simulations, there is an
important trade-off between the result accuracy and the simulation time. In this
Chapter, used platform simulators are available at two abstraction levels [ 1 ]. In
our approach, we combine two simulators during the DSE as follows: first, an
extensive DSE is performed using the fast high-level timed and functional sim-
ulator HLSim [ 2 ] and derives a large set of optimal application configurations,
including execution time and power consumption estimations reported by HLSim;
then, only the interesting configurations are first verified and then explored further
using the more accurate simulator. TLMsim is a SystemC-based cycle-accurate
Transaction-Level Model (TLM) [ 7 ], built using the Synopsys virtual platform
prototyping tools [ 33 ]. This simulator consumes more time, but it reports more
accurate estimations. Recently, simulations based on a cycle-accurate TLM have
gained importance due to standardization efforts.