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while ensuring greater efficiency due to architecture customization and software
compilation techniques.
Design space exploration involves an event-based simulator in the loop. Event-
based simulation still represents a fundamental tool to predict performance of
candidate architectural design points. If we consider cycle-accurate system-level
simulation (where the event corresponds to the completion of a processor clock
cycle), we can have several high-complexity mathematical models to be evaluated
during each event (or clock cycle), leading to an actual evaluation time that can
exceed practical limits for realistic applications. Chip multi-processor architectures
further exacerbate this problem given that the actual simulation speed decreases by
increasing the number of cores of the chip (as shown in Fig. 4.1 ).
While statistical sampling techniques have already been proposed for a single
simulation [ 12 ], design space exploration still lacks of efficient techniques that re-
duce the number of architectural alternatives to be analyzed. To face this problem,
we decided to adopt statistical and machine learning techniques to create a prediction
of the system level metrics for the whole simulation by using closed-form analytical
expressions; the latter are called Response Surface Models (RSM) since they repre-
sent a suitable approximation of the system response under a specific instance of the
input set of parameters (e.g. the system configuration).
This chapter is organized as follows: Sect. 4.2 presents some background on
response surface models while Sect. 4.3 analyzes some of the very peculiar problems
that arise when modeling embedded design spaces. Section 4.4 presents a detailed
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Number of MIPS Cores
Fig. 4.1 SESC [ 15 ] simulation speed when executing the FFT kernel from [ 18 ] by varying the
number of MIPS cores from 1 to 64 (Host machine: two Intel Xeons quad-core at 3 GHz)
 
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