Digital Signal Processing Reference
In-Depth Information
b[0]
x[n]
w[n]
y[n]
input
output
b[1]
a[1]
D
D
b[2]
a[2]
D
D
...
...
...
...
b[K]
a[L]
D
D
Key
D
Data Register (Delay)
Multiplier
Adder
Figure 3.27: General form of the IIR lter.
b
x[n]
y[n]
a
D
Figure 3.28: A simple IIR lter.
