Digital Signal Processing Reference
In-Depth Information
adders, and delay elements. In diagrams showing lters, we show a plus sign within
a circle. Strictly speaking, this is a summation whenever the number of inputs
is greater than two. Architecturally, the summation can be implemented with an
adder tree.
Multipliers are rather complex parts, so sometimes they may be replaced by
simpler parts. For example, to multiply by 8, it is easier to shift the number three
places to the left (since 2
3
= 8). Of course, the drawback here is that a shift register
is not as exible as a multiplier, and this would only work if the value-to-multiply-by
is always a power of 2.
The delay elements can be thought of as registers, in fact, since registers are
used to store a value for a short period of time, a register actually implements a
delay element. Having two registers in a row has the eect of delaying the signal by
two time units. In Figure 3.3, we show this for the general case. The output from
the delay unit(s) appears as a time-shifted version of the input. When the second
input value enters a single delay unit, the rst input value would exit, leading to
x[n] entering on the left and x[n1] exiting on the right. If we consider a group of
k delay units, x[nk] would exit as x[n] enters.
x[n]
x[n−1]
Delay
x[n]
x[n−1]
x[n−2]
Delay
Delay
Figure 3.3: A digital signal, delayed, appears as a time-shifted version of itself.
The name \Finite Impulse Response" comes from the way the lter aects a
signal. An impulse function is an interesting input, where the signal is 0 everywhere,
except for one place where it has the value of 1 (a single unit). An FIR lter's
response to this input is nite in duration, and thus it bears the name Finite Impulse
Response lter.
unit impulse function x[n] = 1, when n = 0
x[n] = 0, when n 6= 0
