Fundamentals - The MPEG - page 42

counting causes the value to reset to zero and begin again. This is known as an overflow . Counting downwards will
achieve the reverse. When zero is reached, subtracting one will cause an underflow where a borrow should be
taken from a bit to the left of the MSB, which does not exist, the result being that the bits which do exist take the
value of all ones, being the highest possible code value.
Figure 2.33: Counting up in a fixed wordlength system leads to overflow (a) where the high-order bit is lost. A
binary counter can be made by cascading divide-by-two stages. Overflow results in wraparound as shown in (c).
Storage devices such as latches can be configured so that they count pulses. Figure 2.33 ( b) shows such an
arrangement. The pulses to be counted are fed to the clock input of a D-type latch, whose input is connected to its
complemented output. This configuration will change state at every input pulse, so that it will be in a true state after
every other pulse. This is a divide-by-two counter. If the output is connected to the clock input of another stage, this
will divide by four. A series of divide- by-two stages can be cascaded indefinitely in this way to count up to
arbitrarily high numbers. Note that when the largest possible number is reached, when all latches are in the high
state, the next pulse will result in all latches going to a low state, corresponding to the count of zero. This is the
overflow condition described above.
Counters often include reset inputs which can be used to force the count to zero. Some are presettable so that a
specific value can be loaded into each latch before counting begins.
As a result of the fixed wordlength, underflow and overflow, the infinite range of real numbers is mapped onto the
limited range of a binary code of finite wordlength. Figure 2.33 ( c) shows that the overflow makes the number scale
circular and it is as if the real number scale were rolled around it so that a binary code could represent any of a
large possible number of real values, positive or negative. This is why the term wrap- around is sometimes used to
describe the result of an overflow condition.
Mathematically the pure binary mapping of Figure 2.33 (c) from an infinite scale to a finite scale is known as modulo
arithmetic. The four-bit example shown expresses real numbers as Modulo-16 codes.
In a practical ADC, each number represents a different analog signal voltage, and the hardware is arranged such
that voltages outside the finite range do not overflow but instead result in one or other limit codes being output. This
is the equivalent of clipping in analog systems. In Figure 2.34 ( a) it will be seen that in an eight-bit pure binary
system, the number range goes from 00 hex, which represents the smallest voltage and all those voltages below it,
through to FF hex, which represents the largest positive voltage and all voltages above it.