Digital Signal Processing Reference
In-Depth Information
damage I/O circuits and shorten the components life. It is often more efficient to set
up and perform this type of analysis in simulation than by performing laboratory
measurements.
Other types of SI analysis include selecting between components to determine
the least expensive device for a particular application and to determine how a prod-
uct can be cost-reduced. For instance, with SI simulations it is easy to decide with
great confidence if an expensive close tolerance termination resistor or expensive
type of decoupling capacitor is required in a particular design. It is also straightfor-
ward to observe the benefits of various circuit board stackups and materials or, in
an ASIC, to select between various I/O drive strengths.
Because well-managed signals generally have lower harmonic content than
poorly terminated signals, a common axiom is that good SI yields good electro-
magnetic interference (EMI) test results. Although good SI is not a guarantee that a
product will flawlessly pass EMI testing, experience shows that favorable EMI test
results are usually significantly less likely when SI problems are present.
In some instances SI simulations are not performed until after the product has
arrived in the laboratory, generally as part of a tardy effort to understand unpre-
dictable system behavior. This can be done on a prototype set aside for debug
purposes or on a device already in production that has been identified by manu-
facturing as having SI problems. Performing an SI analysis this late in the product
design cycle is inefficient and expensive, but it can identify the least costly method
of improving signal quality.
2.3
What Is a Typical Signal Integrity Workfl ow?
An idealized workflow performed by one or more signal integrity engineers is il-
lustrated in Figure 2.1. Although eight distinct phases are shown, adjacent phases
are sometimes merged, and not all projects need to carry out all of these tasks. Ad-
ditionally, the interaction between phases is not shown [for instance, the continual
feedback between debug and design verification testing (DVT)].
During the product's architectural phase, a senior, experienced SI engineer
identifies the limits of technology (such as circuit board size or thickness or ASIC
signaling speeds) and broadly defines the circuitry requiring detailed analysis. New
CAD tools are also evaluated and purchased at this time, including 2D and 3D field
solvers [1]. Decisions are made as to the type of models (transistor level or IBIS
circuit models, lossy transmission line, or S-parameter models, for example) that
will be used. A rough plan describing the power distribution network is developed.
This phase is often merged with the prelayout phase, especially if the design
firm is small (such as a start-up) or has experience with similar technology (and
so already has the critical circuit models), or when the product is not aggressively
pushing new technology.
The prelayout phase is the time when SI models are obtained and validated
and CAD tools are set up. Compatibility between models (verifying that models
from different vendors operate correctly when used in the same simulation) is also
tested [2].
The validation process individually tests the circuit model of each component by
comparing simulation results under simple conditions to laboratory measurements
