Digital Signal Processing Reference
In-Depth Information
Has the weakest driver with the least aggressive rise time that still meets
the timing and receiver noise budgets been selected?
•
Has the effect of many drivers simultaneously switching been simulated?
•
Have the circuit board traces' odd/even modes been properly simulated?
•
Does the simulation include parasitic inductances, capacitance, and resis-
tance for the ASIC package and socket?
•
Does the simulation include some portion of the power distribution net-
work on the ASIC and on the circuit board?
•
Has the case of only one driver switching been simulated?
•
Does the signal rise time become so fast that transmission line effects are
unacceptable?
•
Have the simulations been performed across the full range of voltage, pro-
cess, and junction temperatures?
•
Does the simulation include the effects of manufacturing tolerance and
temperature changes on the board level termination resistors and termina-
tion supply voltages?
•
References
[1]
Dally, W. J., and J. W. Poulton,
Digital Systems Engineering
, Cambridge, U.K.: Cambridge
University Press, 1998.
[2]
Thierauf, S. C.,
High-Speed Circuit Board Signal Integrity
, Norwood, MA: Artech House,
2004.
[3]
Hall, S. H., and H. L. Heck,
Advanced Signal Integrity for High-Speed Digital Designs
,
New York: John Wiley & Sons, 2009.
[4]
Li, P. M.,
Jitter, Noise, and Signal Integrity at High Speed
, Upper Saddle River, NJ: Prentice-
Hall, 2007.
