Digital Signal Processing Reference
In-Depth Information
Proper estimates of component placement are critical for accurate simula-
tion results because the amplitude and timing of reflections depend on the
trace lengths.
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What assumptions have been made regarding termination placement and the
inductance connecting them?
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Component models that include inductance are necessary to obtain the
correct high-frequency behavior.
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Models of vias and any trace connecting the terminators to a power or
ground system must also be included.
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Have the worst-case patterns been identified?
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Were a series of manual simulations run, or was a statistical approach
(such as Monte Carlo) used? What has been done to demonstrate that the
worst-case patterns have actually been found?
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Do the simulations include signal loss, or have lossless lines been assumed?
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Do the simulations include crosstalk effects, or have their effects been ac-
counted for by including a noise “adder”?
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Have models been created for the vias?
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If so, what stackup assumptions have been made?
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What process is in place to ensure that the vias in the actual product match
the mechanical details used in the electrical model?
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15.6
Questions to Ask When Reviewing Postlayout Simulations
Has the layout artwork been fully checked for compliance with the layout
rules?
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Have timing and signal quality simulations been performed with data from
the fully routed circuit board?
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Has the timing on all critical nets been verified?
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Is power supply decoupling adequate and is the capacitor placement and
layout optimal?
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Verify that ASIC manufacturers' guidelines have been followed for the
placement and values of decoupling capacitors.
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Are previously unsimulated stubs present on any net, especially high-speed
nets?
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If long enough, stubs will create reflections that can interfere with proper
signaling.
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Do the postroute SI simulations include the actual number of layer changes?
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Vias increase signal loss and can cause reflections. Ensure that the actual
layout matches the simulation model.
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Is the location of series or parallel termination resistors acceptable?
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Does it match the simulations?
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Do the simulations include the range of trace lengths and the impedance of
the traces connecting the terminators?
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