Digital Signal Processing Reference
In-Depth Information
be corrected. However, sometimes signals are intentionally underdriven to remove
high-frequency harmonics as a way to reduce EMI and to save power in low-power
applications.
Overdriven signals are sharp edged and overshoot past the static high value.
The overshooting may be severe enough for the signal to momentarily fall (to ring
back) below the receiver switch point before it settles at the steady state value. For
large overdrive conditions the signal may oscillate multiple times between succes-
sively smaller overshoot and ringback values before it finally comes to rest at a
steady state value.
Therefore, the following questions should be asked when reviewing signal in-
tegrity simulations:
What analysis was performed to guarantee that both the worst-case under-
drive and worst-case overdrive situations have been identified?
•
In some systems the difference in signal quality between these two will be
small, but usually the difference is demonstrable.
•
In CMOS systems underdrive is usually the worst when the slowest pro-
cess corner is used at the highest temperature and lowest power supply
voltage and the highest series resistance (if the signal is series terminated).
•
In CMOS systems worst-case overdrive usually occurs when the fastest
process corner is used at the highest voltage and lowest temperature. If
series terminated, the minimum resistance value is used.
•
If the signal experiences ringback, has its impact on system timing been thor-
oughly analyzed?
•
For example, a worst case may be for a data strobe or clock to overshoot
(and reach the switch point sooner than expected) while the data signal
its clocking is underdriven and so only gradually reaches the switch point.
•
If the signal overshoots, does the peak value remain within the manufac-
turer's safe values specification?
•
If the signal is underdriven, how has the effect of power supply noise or noise
on adjacent signals been tested?
•
Since underdriven signals only gradually reach the receiver switch point,
they are especially vulnerable to false triggering caused by crosstalk or by
noise coupled to the signal from the power supply.
•
Have all the sources of signal coupling been identified and included in the
simulation?
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See the earlier discussion on crosstalk.
•
Have the worst-case data patterns been identified?
•
The worst-case switching pattern depends on the exact circumstances of
the design, but in general, a simple 1/0 “square wave” pattern is usually
not the worst case. Often the worst pattern involves timing the transmis-
sion of a bit so that it combines with energy still present on the line, but
the “lone one” [1, 2] can also be significant, especially in situations where
the line is lossy.
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