Digital Signal Processing Reference
In-Depth Information
75
High impedance
caused by probe
inductance
40 mil pad with 60 mil antipad
50
43
Ω
40 mil pad with 45 mil antipad
32
Ω
25
200 ps
400 ps
600 ps
Figure 14.10
TDR showing that a via with large antipad has higher impedance than one with a
small antipad. (
From:
[24]. Used with permission.)
The added capacitance of these pads lower the via impedance, which can cause
significant reflections when signaling at high speeds. The circuit board manufac-
turer can be requested to remove nonfunctional pads from those nets carrying high
data rate signals, but they should confirm that the board reliability will not be un-
duly impacted. Removal is done by the circuit board manufacturer and not in the
artwork by the layout designer.
14.5.6 Can the Via Impedance Be Adjusted?
The impedance of a signal carrying via can be controlled by the careful placement of
return path vias near the signal carrying via [27, 28]. This technique is of most use
when signaling at high data rates and requires the use of a 3D field solver to adjust
the placement of the vias and to select the pad and antipad sizes.
14.5.7 What Are Differential Vias?
A typical via presents a problem when differential signals change layers because the
via pair will not have the same differential impedance as the traces.
To correct this, a pair of vias can be designed for a specific differential imped-
ance [29, 30] by adjusting their spacing and dimensions and occasionally even the
antipad shape. This is best done with a 3D field solver.
An example of a differential via appearing in a 3D field solver is shown in
Figure 14.11.
Coupling between the vias occurs in the region between the planes, so no other
structures (such as vias, microvias, traces, or nonplated holes) can be placed be-
tween the via pair. It is also important that other vias (including nonplated holes
